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Threads run on a fixed number of core processors, sharing the memory units, such as lookup trees, instruction memory, and global packet buffers. An alternative to run-to-completion is the pipeline model. Here, the forwarding process is divided into different stages, and each stage is handled by another core processor with its own instruction memory [24]. 22 A. Kind, R. Pletka, and M. Waldvogel Appl Interfaces Network Services APIs Network . . . . . Appl Control Ingress Data . . Ingress Management Node Services APIs Switch Fabric Network Processor Network Processor Egress Egress Control Processor .

Paxson. Stream Control Transmission Protocol. RFC 2960, IETF, Oct. 2000. 23. D. L. Tennenhouse and D. J. Wetherall. Towards an active network architecture. ACM Computer Communication Review, 26(2):5–18, Apr. 1996. 24. M. Venkatachalam, P. Chandra, and R. Yavatkar. A highly flexible, distributed multiprocessor architecture for network processing. Computer Networks, 41(5):563–586, Apr. 2003. 25. T. Wolf and J. Turner. Design issues for high-performance active routers. IEEE Selected Areas in Communications, 19(3):404–409, Mar.

18 in which the ARB is installed. The ARB operates at 64b/66MHz PCI speed. 600 Theoretical transfer rate Measured transfer rate RTT 400 200 0 100000 Packets sent [pps] 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 1e+06 1000 600 400 Theoretical transfer rate Measured transfer rate RTT 200 0 100000 Packets sent [pps] (a) 72B/packet, PromethOS/host CPU 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 1e+06 (b) 1460B/packet, PromethOS/host CPU 1000 100 1000 80 800 80 800 60 600 60 600 40 20 Theoretical transfer rate Measured transfer rate RTT 0 100000 Packets sent [pps] 400 200 0 1e+06 (c) 72B/packet, PromethOS/ePPC Transfer rate [mbps] 100 RTT [µs] Transfer rate [mbps] 800 40 20 400 Measured transfer rate RTT 0 100000 Packets sent [pps] RTT [µs] 800 Transfer rate [mbps] Transfer rate [mbps] 1000 RTT [µs] L.

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